The desire for increased production or workload in a microprocessor platform needs to be balanced with the management of power consumption by that platform. This includes controlling the peak power demands of that microprocessor platform. Existing solutions to workload and power management exploiting mutually exclusive activation of resources or token-based control and power shifting across processor and memory resources, depending on whether the workload phase is central processing unit (CPU) bound or memory-bound. Both of these methods, however, have limitations on their implementations and ability to provide the desired level of workload and power management.
Information about mutually exclusive regions of the logic requires significant analysis, which is hard to automate in tool form. The information has to be generally gleaned manually from designer knowledge. In some implementations, the opportunities for absolute mutual exclusion are quite small, unless the designer is aware from the beginning about the plan to use this style of peak power control. Similarly, the token-based control of peak power requires careful analysis to make sure that the algorithm for token allocation and de-allocation does not hurt system performance in a significant manner. There is no straightforward, simple rule of thumb that would allow one to assess the performance cost of enforcing peak power using these two methods. This makes it hard to commit such power control algorithms to hardware, since some workloads may experience unpredictably large performance hits.
Power shifting across CPU and memory resources capitalizes on the observation that workloads often go through alternate durations of CPU-bound and memory-bound behavior. However, if each processor core supports n-way multithreading, e.g., simultaneous multithreading (SMT), where “n” may be as large as 8, the probability of all 8 threads in a core moving from CPU-bound mode to memory-bound mode and vice versa in synchrony is rather small in the general case. Hence, the opportunity of power savings may become rather small if this is the only actuator that is used to shift power across distinct resource regions while maintaining a power cap. Also, in both of the prior systems for power management, the primary hardware mechanisms used to disable or throttle a resource when shifting power elsewhere are actuators like clock-gating, power-gating, dynamic voltage and frequency scaling (DVFS) or fetch throttling. Opportunities for getting such actuators engaged for power reduction are very limited in n-way multithreaded cores where “n” is large (e.g. 4 or 8).
Other related methods for peak power management fail to work very well in the presence of heavily multithreaded processor cores. As such, there is a need for peak power control systems and methods that work well for modern multi-core microprocessors in which significant levels of multithreading are supported for every core in order to maximize the microprocessor's workload throughput performance for a given area and power budget.